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The following archive was created by hippie-mail 7.98617-22 on Sat Apr 10 1999 - 01:17:37
Alex Alten (Alten@Home.Com)
Fri, 11 Dec 1998 08:38:54 -0800
At 09:27 AM 12/11/98 -0500, Sandy Harris wrote:
>Andy Brown wrote:
>>
>> You wrote:
>>
>> > I assume that a hand optimized ASM implementation for AMD K6 will
>> > run faster than a similar P-II implementation. The reason? Simply
>> > because the K6 is more efficient in Operations/Clock ... specially
>> > working with integers where the lack of the L2 is not relevant.
>>
>> Only if you can keep everything in registers. The 512K clk/2 L2 cache
>> on a PII will easily trounce a K6 if you have to go out to memory a
>> lot. The PPro is even better at this, and the K6-3 will beat them all
>> early next year.
>
>For most applications, you'd be right. But for most crypto algorithms,
>code & tables would fit in level 1 cache & the data has to be read from
>memory once & written back once no matter what cache you have, so the
>level 2 cache is less of an issue.
>
Right. Also I've found that the associativity of the cache makes a huge
difference in performance, at least for our cryptography. The K6 is only
2-way while the PPro is 4 way. The MMX extensions of PII help a bit (about
25%), it is nice to have the extra registers (makes code simpler). I
expect the 3 ALU's in the K7 will add 50% speed to our performance, we
scale almost linearly with the number of ALU's.
- Alex
--Alex Alten
Alten@Home.Com Alten@TriStrata.Com
P.O. Box 11406 Pleasanton, CA 94588 USA (925) 417-0159
The following archive was created by hippie-mail 7.98617-22 on Sat Apr 10 1999 - 01:17:37