Ernest Hua (Hua@teralogic-inc.com)
Fri, 19 Jun 1998 11:48:34 -0700
Are there public domain tools to compile/program FPGA's/PLD's?
Do companies like Altera/Xilinx/Atmel publish enough programming specs
to develop tools/compilers?
Ern
-----Original Message-----
From: Trei, Peter [SMTP:ptrei@securitydynamics.com]
Sent: Friday, June 19, 1998 6:59 AM
To: 'Tim Dierks'; CodherPlunks@toad.com
Subject: RE: ASIC price/volume/performance
Tim writes:
> -----Original Message-----
> From: Tim Dierks [SMTP:tim@dierks.org]
> Sent: Thursday, June 18, 1998 9:18 PM
> [I originally sent this to cryptography@c2.net, but it seems
to be down]
>
> Upon finding the following messages, I checked the Wiener
paper;
> apparently, the chip he specifies there is about 26,000
equivalent gates;
> if you can save 4% on that design, you can get two on one of
these chips.
> If they'll run at 200 MHz, each chip can check 400 million
keys per
> second.
> This means each chip is more than 11 times as fast as the
entire
> distributed.net effort's peak speed. At the prices below you
could build
> the following DES engines:
[...]
[Trei, Peter]
Response:
Check your numbers. The distributed.net site has
extensive statistics. The current estimated rate
if they switched over to DES is around 66 Gk/sec,
which is about 165 times the rate of your
hypothetical chip.
Wiener has publised an update to his paper, utilizing
Moore's Law to speed up his chips by a factor of 4.
The next RSA Labs DES challenge starts on the
13th of July. If d.n manages to achieve the
above rate (and I think they will), they will
exhaust the keyspace in 12.6 days. This gives
them an excellent chance of finding the key
within the 10 days required for the $10k
prize, and a certainty of winning $5k, unless
someone else gets there first. To the best of
my knowledge, no one has publically announced
an effort which even approaches d.n's keyrate.
> Peter Trei
ptrei@securitydynamics.com
The following archive was created by hippie-mail 7.98617-22 on Fri Aug 21 1998 - 17:18:45 ADT