Tim Dierks (tim@dierks.org)
Thu, 18 Jun 1998 18:18:13 -0700
[I originally sent this to cryptography@c2.net, but it seems to be down]
Upon finding the following messages, I checked the Wiener paper;
apparently, the chip he specifies there is about 26,000 equivalent gates;
if you can save 4% on that design, you can get two on one of these chips.
If they'll run at 200 MHz, each chip can check 400 million keys per second.
This means each chip is more than 11 times as fast as the entire
distributed.net effort's peak speed. At the prices below you could build
the following DES engines:
Time to break (average) Chip Count Total price for chips
25 hours 1000 $5,000
5 hours 5000 $17,500
2.5 hours 10000 $27,500
30 minutes 50000 $115,000
The Weiner specification involves chips which are one-fourth as fast (50
MHz), have one engine per chip and cost $10.50 each. When you build a
single "frame" of his design using this chip speed and cost, you end up
with a complete frame for $59,280 which has 5,760 chips in it and tests
keys at the rate of 2.3e12 keys/second, for an average break time of 4
hours, 21 minutes. This includes parts and fabrication, but not design.
This is an improvement of approximately 13.4 times in price/performance
over Wiener's paper of August 1993. I have assumed no cost reduction for
any part other than the keysearch chips, which represent 61% of the cost of
the original frame, but only 34% of the current frame price.
I don't know if the guys below are for real or not, but this would seem to
imply that any bozo with ASIC design knowledge, a few months of weekends,
and $60K can crack a DES key in an afternoon.
- Tim
>Date: 9 Jun 1998 20:39:14 GMT
>From: "kash" <kash@ix.netcom.com>
>Subject: BREAKTHROUGH ASIC PRODUCT---Beta customers needed
>
>We are developing a novel ASIC Technology which will allow low cost
>prototyping for ASIC designs in the 20K gate to 500K gate range.
>
>We are looking for Beta customers who will recieve preferential pricing.
>
>Key Product Features:
>
>Zero NRE.
>3.3V operation with 5V tolerant inputs.
>20K gates to 500K gates.
>RAM with 200Mhz cycle times.
>Gate delays of 100 picoseconds.
>
>Minimum volumes are 1000 pcs/yr.
>
>We are also looking for designers who wish to become third party design
>center consultants on a world-wide basis. FPGA and ASIC expertise required.
>
>For further details:
>
>E-mail me: kash@ix.netcom.com
>or call: 408 360 0430
>or fax: 408 360 0435
>
>Regards,
>
>Kash Johal
>Date: 10 Jun 1998 22:52:43 GMT
>From: "kash johal" <kash@ix.netcom.com>
>Subject: Re: BREAKTHROUGH ASIC PRODUCT---Beta customers needed
>
>Peter,
>
>I think you are mistaken about other vendors offering this
>price/performance.
>
>Our smallest device is approx 50K useable gates, so we can mux in several
>customer codes in the 5K used gate range. Our technology is 0.35 micron
>Drawn with 100 ps gate delays.
>
>In a Pq44 package our volume prices would be:
>
>1k $5.00
>5K $3.50
>10K $2.75
>50K $2.30
>100K $2.00
>1M+ $1.50
>
>Customers can get to the 50K price for exanple with 10 designs averaging 5K
>pcs.
>
>Also remember the devices do not require external memory configuration,
>will run at 200-300Mhz, and are true ASIC gate counts.
>
>Welcome your thoughts and comments,
>
>Regards,
>
>Kash
>
>Peter <z80@ds1.com> wrote in article
><3581436f.39407184@news.netcomuk.co.uk>...
>> Lots of people offer this. It is the unit cost that makes or breaks
>> this. What would be the cost of a 5k gate device, in a QFP-44, 1k and
>> 5k pieces? From a Xilinx XNF netlist, and with production test vectors
>> supplied in a text format?
>>
>> Peter.
>>
>> Return address is invalid to help stop junk mail.
>> E-mail replies to zX80@digiYserve.com but
>> remove the X and the Y.
>>
Tim Dierks - Software Haruspex - tim@dierks.org
"Well, cyberterrorists may be difficult to capture in the act, but from what I
know about people who are highly skilled with computers, they should be easy
to beat up." - Ernest Cey, quoted in The Onion, <http://www.theonion.com>
The following archive was created by hippie-mail 7.98617-22 on Fri Aug 21 1998 - 17:18:42 ADT